MSTAR/MTK的TV/Monitor芯片是目前市场显示设备的主流，市占率六成以上。为了方便广大开发者，笔者整理了MSTAR/MTK屏参变量和寄存器的对应关系，如下：
1： const char *m_pPanelName;
PanelName 屏的名称
2： MS_U8 m_bPanelDither :1;
REG_SC_BK10_1B_L, bPanelDither =1Æ0X2D05, bPanelDither
=0Æ0X2D00
3: APIPNL_LINK_TYPE m_ePanelLinkType :4;
REG_SC_BK10_22_L , LVDS =0x11, RSDS =0x00
4: m_bPanelDualPort :1;
REG_SC_BK10_21_L[8], REG_MOD_BK00_4A_L[8],
5: MS_U8 m_bPanelSwapPort :1;
REG_MOD_BK00_4A_L[0]
6: MS_U8 m_bPanelSwapOdd_ML :1;
REG_MOD_BK00_49_L[12]
7: MS_U8 m_bPanelSwapEven_ML :1;
REG_MOD_BK00_49_L [14]
8 : MS_U8 m_bPanelSwapOdd_RB :1;
REG_MOD_BK00_49_L [11]
9: MS_U8 m_bPanelSwapEven_RB :1;
REG_MOD_BK00_49_L [13]
11: MS_U8 m_bPanelSwapLVDS_POL :1;
REG_MOD_BK00_40_L [5]
12: MS_U8 m_bPanelSwapLVDS_CH :1;
REG_MOD_BK00_40_L [6]
13: MS_U8 m_bPanelPDP10BIT :1;
REG_MOD_BK00_40_L [3]
14: MS_U8 m_bPanelLVDS_TI_MODE :1;
REG_MOD_BK00_40_L [2], 说明当前的 panel 是不是 TI mode
15: MS_U8 m_ucPanelDCLKDelay;
REG_MOD_BK00_40_L [8:11],
16: MS_U8 m_bPanelInvDCLK :1;
REG_MOD_BK00_4A_L [4],
17: MS_U8 m_bPanelInvDE :1;
REG_MOD_BK00_4A_L [2],
18: MS_U8 m_bPanelInvHSync :1;
REG_MOD_BK00_4A_L [12]
19: MS_U8 m_bPanelInvVSync :1;
REG_MOD_BK00_4A_L [3],
20: MS_U8 m_ucPanelDCKLCurrent;
REG_SC_BK10_47_L [6:7],
21: MS_U8 m_ucPanelDECurrent;
REG_SC_BK10_47_L [4:5],
22: MS_U8 m_ucPanelODDDataCurrent;
REG_SC_BK10_47_L [2:3]
23:MS_U8 m_ucPanelEvenDataCurrent;
REG_SC_BK10_47_L [0:1]
24: MS_U16 m_wPanelOnTiming1;
NOT USE time between panel & data while turn on power
25: MS_U16 m_wPanelOnTiming2;
NOT USE time between data & back light while turn on power
26: MS_U16 m_wPanelOffTiming1;
NOT USE time between back light & data while turn off power
27: MS_U16 m_wPanelOffTiming2;
NOT USE time between data & panel while turn off power
28: MS_U8 m_ucPanelHSyncWidth;
REG_SC_BK10_01_L [7:0]
29: MS_U8 m_ucPanelHSyncBackPorch;
no register setting, provide value for query only, not support Manuel VSync
Start/End now
30: MS_U8 m_ucPanelVSyncWidth;
MS_U8 m_ucPanelVBackPorch;
REG_SC_BK10_02_L [10:0] ÆVSync start = Vtt - VBackPorch – VsyncWidth,
REG_SC_BK10_02_L [10:0] ÆVSync end = Vtt – VbackPorch
31: MS_U16 m_wPanelHStart;
REG_SC_BK10_04_L [11:0],
DE H Start (PANEL_HSYNC_WIDTH + PANEL_HSYNC_BACK_PORCH)
32: MS_U16 m_wPanelVStart;
REG_SC_BK10_06_L [11:0]
33: MS_U16 m_wPanelWidth;
REG_SC_BK10_05_L [11:0] Æ HEnd = HStart + Width - 1
34 :MS_U16 m_wPanelHeight;
REG_SC_BK10_05_L [11:0]Æ Vend = VStart + Height - 1
35: MS_U16 m_wPanelMaxHTotal;
NOT USE Reserved for future using
36: MS_U16 m_wPanelHTotal;
REG_SC_BK10_0C_L [11:0]
37: MS_U16 m_wPanelMinHTotal;
NOT USE Reserved for future using.
38: MS_U16 m_wPanelMaxVTotal;
NOT USE Reserved for future using.
39: MS_U16 m_wPanelVTotal;
REG_SC_BK10_0D_L [11:0]
40: MS_U16 m_wPanelMinVTotal;
NOT USE Reserved for future using.
41: MS_U8 m_dwPanelMaxDCLK;
NOT USE Reserved for future using.
42: MS_U8 m_dwPanelDCLK;
REG_BK1031_0F[23:0] ,{0x1031_10[7:0], 0x1031_0F[15:0]}
DefaultVFreq=dwPanelDCLK*10000000)/(m_wPanelHTotal*m_wPanelVTotal);
43: MS_U8 m_dwPanelMinDCLK;
NOT USE Reserved for future using.
44: MS_U16 m_wSpreadSpectrumStep;
MS_U16 m_wSpreadSpectrumSpan;
Not USE Move to board define
45: MS_U8 m_ucDimmingCtl;
MS_U8 m_ucMaxPWMVal;
MS_U8 m_ucMinPWMVal;
Initial Dimming Value/ Max Dimming Value/ Min Dimming Value
46: MS_U8 m_bPanelDeinterMode :1;
NOT USE
47: E_PNL_ASPECT_RATIO m_ucPanelAspectRatio;
Panel Aspect Ratio, provide information to upper layer application for aspect
ratio setting.
48: MS_U16 m_u16LVDSTxSwapValue;
REG_MOD_BK00_73_L [0:15],
49: APIPNL_TIBITMODE m_ucTiBitMode;
REG_MOD_BK00_4B_L [1:0], 当颜色不对的时候，就可以调整这个设定来
试验。
50: APIPNL_OUTPUTFORMAT_BITMODE m_ucOutputFormatBitMode;
REG_MOD_BK00_49_L [6:7], 10: 8bit, 01: 6bit  ther 10bit
Define panel output format bit mode. The default value is 10bit, becasue 8bit
panel can use 10bit config and 8bit config. But 10bit panel(like PDP panel) can
only use 10bit config. And some PDA panel is 6bit
51: MS_U8 m_bPanelSwapOdd_RG :1;
MS_U8 m_bPanelSwapEven_RG :1;
MS_U8 m_bPanelSwapOdd_GB :1;
MS_U8 m_bPanelSwapEven_GB :1;
REG_MOD_BK00_49_L [2:5], Odd_RG: bit3, Odd_GB: bit2 , Even_RG bit5,
Even_GB bit4
52: MS_U8 m_bPanelDoubleClk :1;
REG_LPLL_03[7] ,LVDS dual mode
56: MS_U32 m_dwPanelMaxSET;
MS_U32 m_dwPanelMinSET;
这个值会限定 FPLL LOCK 的范围，也就是 LPLL_D5D6D7
57: APIPNL_OUT_TIMING_MODE m_ucOutTimingMode;
Define which panel output timing change mode is used to change VFreq for
same panel, 目前有三种选择 E_PNL_CHG_DCLK，E_PNL_CHG_HTOTAL，
E_PNL_CHG_VTOTAL ， 后面两者都是为了保持 DCLK 不变而修改
HTOTAL/VTOTAL.
58: MS_U8 m_bPanelNoiseDith :1;
REG_SC_BK24_3F_L [3]
Note 以上寄存器都是 16bit Address
MOD: BK1032
LPLL: BK1031
对应MSTV_Tool.exe界面如下：
C:\Users\ALEXWE~1.SMA\AppData\Local\Temp\企业微信截图_16419608124291.png
|
|
